US 11,908,905 B2
Electrode structure for vertical group III-V device
Yao-Chung Chang, Zhubei (TW); Chun Lin Tsai, Hsin-Chu (TW); Ru-Yi Su, Kouhu Township (TW); Wei Wang, Taipei (TW); and Wei-Chen Yang, Taoyuan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 18, 2022, as Appl. No. 17/867,012.
Application 17/867,012 is a division of application No. 16/884,292, filed on May 27, 2020, granted, now 11,450,749.
Prior Publication US 2022/0352325 A1, Nov. 3, 2022
Int. Cl. H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/778 (2006.01); H01L 29/868 (2006.01)
CPC H01L 29/417 (2013.01) [H01L 29/41741 (2013.01); H01L 29/6609 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/7788 (2013.01); H01L 29/868 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
forming a buffer layer over a substrate;
forming an active layer on the buffer layer;
forming a top electrode on the active layer; and
performing an etch process on the buffer layer and the substrate to define a plurality of pillar structures, wherein the plurality of pillar structures comprise a first pillar structure laterally offset from a second pillar structure, wherein at least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode, wherein the etch process is performed while the top electrode is disposed on the active layer.