US 11,908,903 B2
Process window control for gate formation in semiconductor devices
Kuei-Yu Kao, Hsinchu (TW); Shih-Yao Lin, New Taipei (TW); Chen-Ping Chen, Toucheng Township (TW); Chih-Han Lin, Hsinchu (TW); Ming-Ching Chang, Hsinchu (TW); and Chao-Cheng Chen, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jul. 8, 2021, as Appl. No. 17/370,750.
Prior Publication US 2023/0008921 A1, Jan. 12, 2023
Int. Cl. H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/401 (2013.01) [H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/66484 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor structure, comprising:
removing a portion of an active channel structure to form a recess;
filling the recess with dielectric material;
forming a cladding layer adjacent the active channel structure but not adjacent the dielectric material;
forming a gate structure around the active channel structure, wherein the gate structure comprises an active gate structure;
forming a dummy gate structure around the active channel structure; and
removing the dummy gate structure before forming the active gate structure.