US 11,908,891 B2
High voltage device with gate extensions
Jhih-Bin Chen, Hsinchu (TW); and Ming Chyi Liu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 2, 2022, as Appl. No. 17/734,344.
Application 17/734,344 is a division of application No. 16/921,075, filed on Jul. 6, 2020, granted, now 11,329,128.
Claims priority of provisional application 62/893,340, filed on Aug. 29, 2019.
Prior Publication US 2022/0262899 A1, Aug. 18, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0653 (2013.01) [H01L 29/0692 (2013.01); H01L 29/0873 (2013.01); H01L 29/7825 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of forming an integrated chip, comprising:
forming a plurality of separate isolation structures within a substrate, wherein the plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another by the substrate;
selectively etching the substrate to form a gate base recess within the substrate, the gate base recess extending past the outermost sidewalls of the plurality of separate isolation structures;
selectively etching the plurality of separate isolation structures to form a plurality of gate extension trenches extending outward from the gate base recess;
forming a conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode; and
forming a source region and a drain region on opposing sides of the gate electrode.