CPC H01L 29/0653 (2013.01) [H01L 29/0692 (2013.01); H01L 29/0873 (2013.01); H01L 29/7825 (2013.01)] | 20 Claims |
1. A method of forming an integrated chip, comprising:
forming a plurality of separate isolation structures within a substrate, wherein the plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another by the substrate;
selectively etching the substrate to form a gate base recess within the substrate, the gate base recess extending past the outermost sidewalls of the plurality of separate isolation structures;
selectively etching the plurality of separate isolation structures to form a plurality of gate extension trenches extending outward from the gate base recess;
forming a conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode; and
forming a source region and a drain region on opposing sides of the gate electrode.
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