US 11,908,866 B2
Gate structures having neutral zones to minimize metal gate boundary effects and methods of fabricating thereof
Chia-Hao Pao, Kaohsiung (TW); Chih-Hsuan Chen, Hsinchu (TW); Lien Jung Hung, Taipei (TW); and Shih-Hao Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on May 9, 2022, as Appl. No. 17/739,758.
Application 17/739,758 is a division of application No. 16/678,695, filed on Nov. 8, 2019, granted, now 11,329,042.
Claims priority of provisional application 62/773,549, filed on Nov. 30, 2018.
Prior Publication US 2022/0262799 A1, Aug. 18, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/82385 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 29/4236 (2013.01); H01L 29/4238 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 27/092 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
removing a dummy gate to form a gate trench in a gate structure, wherein the gate structure includes a first transistor region that corresponds with a first transistor, a second transistor region that corresponds with a second transistor, and a boundary region disposed between the first transistor region and the second transistor region;
forming a gate dielectric layer in the gate trench in the first transistor region, the second transistor region, and the boundary region;
forming a p-type work function layer in the gate trench over the gate dielectric layer in the first transistor region, the second transistor region, and the boundary region, wherein the p-type work function layer has a first thickness in the first transistor region, a second thickness in the second transistor region, and a third thickness in the boundary region, wherein the p-type work function layer and the gate dielectric layer fill the gate trench in the boundary region; and
forming an n-type work function layer in the gate trench over the p-type work function layer in the first transistor region and the second transistor region.