CPC H01L 24/83 (2013.01) [H01L 23/5283 (2013.01); H01L 24/27 (2013.01); H01L 24/32 (2013.01); H01L 2224/2784 (2013.01); H01L 2224/27452 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/83201 (2013.01); H01L 2924/37001 (2013.01)] | 20 Claims |
1. A method comprising:
performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure;
performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition;
planarizing the first bonding layer;
forming a second bonding layer over a second substrate;
pressing the second bonding layer onto the first bonding layer; and
removing the first substrate.
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