US 11,908,829 B2
Integrated circuit package and method of forming same
Yao-Te Huang, Hsinchu (TW); Hong-Wei Chan, Hsinchu (TW); and Yung-Shih Cheng, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 17, 2021, as Appl. No. 17/350,856.
Claims priority of provisional application 63/166,532, filed on Mar. 26, 2021.
Prior Publication US 2022/0310556 A1, Sep. 29, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/528 (2006.01)
CPC H01L 24/83 (2013.01) [H01L 23/5283 (2013.01); H01L 24/27 (2013.01); H01L 24/32 (2013.01); H01L 2224/2784 (2013.01); H01L 2224/27452 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/83005 (2013.01); H01L 2224/83201 (2013.01); H01L 2924/37001 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
performing a first plasma deposition to form a buffer layer over a first side of a first integrated circuit device, the first integrated circuit device comprising a first substrate and a first interconnect structure;
performing a second plasma deposition to form a first bonding layer over the buffer layer, wherein a plasma power applied during the second plasma deposition is greater than a plasma power applied during the first plasma deposition;
planarizing the first bonding layer;
forming a second bonding layer over a second substrate;
pressing the second bonding layer onto the first bonding layer; and
removing the first substrate.