US 11,908,818 B2
Semiconductor device
Sheng-Yu Wu, Hsinchu (TW); Ching-Hui Chen, Hsinchu (TW); Mirng-Ji Lii, Hsinchu County (TW); Kai-Di Wu, Tainan (TW); Chien-Hung Kuo, Tainan (TW); Chao-Yi Wang, Tainan (TW); Hon-Lin Huang, Hsinchu (TW); Zi-Zhong Wang, Tainan (TW); and Chun-Mao Chiu, Kaohsiung (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Nov. 12, 2021, as Appl. No. 17/525,593.
Application 16/436,795 is a division of application No. 15/715,659, filed on Sep. 26, 2017, granted, now 10,319,695, issued on Jun. 11, 2019.
Application 17/525,593 is a continuation of application No. 16/436,795, filed on Jun. 10, 2019, granted, now 11,177,228.
Claims priority of provisional application 62/526,980, filed on Jun. 29, 2017.
Prior Publication US 2022/0077094 A1, Mar. 10, 2022
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/13 (2013.01) [H01L 24/08 (2013.01); H01L 24/11 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13155 (2013.01); H01L 2924/13091 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate;
a conductive pad over the semiconductor substrate;
a conductive bump over the conductive pad, wherein the conductive bump has a stepped sidewall structure including a lower sidewall, an upper sidewall laterally offset from the lower sidewall, and an intermediary surface laterally extending from a bottom edge of the upper sidewall to a top edge of the lower sidewall, the conductive bump has a bottom portion over the conductive pad and a top portion over the bottom portion;
a conductive cap over the conductive bump, wherein the bottom portion of the conductive bump is wider than the conductive cap and the top portion of the conductive bump; and
a passivation layer over the semiconductor substrate and laterally surrounding the conductive bump, wherein the passivation layer has a top surface higher than the intermediary surface of the stepped sidewall structure of the conductive bump and lower than a top surface of the conductive cap.