US 11,908,800 B2
Semiconductor structure
Ya-Chin Chiu, Taichung (TW); Ming-Hsien Lin, Taichung (TW); Chia-Tung Hsu, Taichung (TW); and Lun-Chieh Chiu, Miaoli County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 22, 2022, as Appl. No. 17/871,738.
Application 17/871,738 is a division of application No. 17/160,251, filed on Jan. 27, 2021, granted, now 11,515,256.
Prior Publication US 2022/0367377 A1, Nov. 17, 2022
Int. Cl. H01L 23/532 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/53266 (2013.01) [H01L 21/76846 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure comprising:
a multi-level interconnect structure;
a passivation layer above the multi-level interconnect structure;
a barrier layer lining an inner sidewall of the passivation layer, a top surface of the passivation layer and a top surface of a conductive line of the multi-level interconnect structure, wherein the barrier layer comprises:
a first layer in a nano-crystalline phase;
a second layer above the first layer and in an amorphous phase;
a third layer above the second layer and in a polycrystalline phase; and
a fourth layer above the third layer and in a nano-crystalline phase; and
a pad layer above the barrier layer.