US 11,908,797 B2
Integrated circuit device having a bit line and a main insulating spacer with an extended portion
Jiyoung Ahn, Seoul (KR); Seunguk Han, Suwon-si (KR); Sunghwan Kim, Yeongcheon-si (KR); Seoryong Park, Ansan-si (KR); Kiseok Lee, Seoul (KR); Yoonyoung Choi, Seoul (KR); Taehee Han, Hwaseong-si (KR); and Jiseok Hong, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 21, 2020, as Appl. No. 17/129,083.
Claims priority of application No. 10-2020-0073249 (KR), filed on Jun. 16, 2020.
Prior Publication US 2021/0391259 A1, Dec. 16, 2021
Int. Cl. H01L 23/528 (2006.01); H01L 29/06 (2006.01); H10B 12/00 (2023.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 21/764 (2006.01)
CPC H01L 23/5283 (2013.01) [H01L 21/764 (2013.01); H01L 21/7682 (2013.01); H01L 29/0649 (2013.01); H10B 12/482 (2023.02); H10B 12/485 (2023.02); H10B 12/488 (2023.02); H01L 23/5222 (2013.01); H10B 12/0335 (2023.02); H10B 12/315 (2023.02); H10B 12/34 (2023.02)] 17 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a bit line on a substrate, the bit line comprising a lower conductive layer and an upper conductive layer;
an insulating capping pattern on the bit line; and
a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer comprising an extended portion opposite the upper conductive layer, the extended portion protruding toward the upper conductive layer compared to a portion of the main insulating spacer opposite the lower conductive layer,
wherein the extended portion of the main insulating spacer fills an undercut space corresponding to a sidewall of the upper conductive layer and a bottom surface of the insulating capping pattern, and
wherein the extended portion of the main insulating spacer and the portion of the main insulating spacer opposite the lower conductive portion form a continuous portion of a common material.
 
10. An integrated circuit device comprising:
a bit line comprising a lower conductive layer and an upper conductive layer on the lower conductive layer in a vertical direction, the lower conductive layer being on a substrate and the upper conductive layer having a width less than a width of the lower conductive layer in a horizontal direction;
an insulating capping pattern on the upper conductive layer in the vertical direction, the insulating capping pattern having a width greater than the width of the upper conductive layer in the horizontal direction; and
a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer comprising an extended portion that is convex toward the upper conductive layer,
wherein the width of the upper conductive layer in the horizontal direction varies along the vertical direction.
 
14. An integrated circuit device comprising:
a substrate comprising a plurality of active regions apart from each other, the plurality of active regions comprising a first active region and a second active region adjacent to the first active region;
a bit line connected to the first active region and comprising a lower conductive layer and an upper conductive layer stacked on the substrate in a vertical direction;
an insulating capping pattern on the bit line;
a contact plug adjacent to the bit line in a horizontal direction, the contact plug being connected to the second active region; and
a spacer structure between the bit line and the contact plug,
wherein the spacer structure comprises a main insulating spacer comprising an extended portion opposite the upper conductive layer, the extended portion protruding toward the upper conductive layer compared to a portion of the main insulating spacer opposite the lower conductive layer,
wherein the extended portion of the main insulating spacer fills an undercut space corresponding to a sidewall of the upper conductive layer and a bottom surface of the insulating capping pattern, and
wherein the extended portion of the main insulating spacer and the portion of the main insulating spacer opposite the lower conductive portion form a continuous portion of a common material.