US 11,908,794 B2
Protection liner on interconnect wire to enlarge processing window for overlying interconnect via
Shin-Yi Yang, New Taipei (TW); Hsin-Yen Huang, New Taipei (TW); Ming-Han Lee, Taipei (TW); Shau-Lin Shue, Hsinchu (TW); Yu-Chen Chan, Taichung (TW); and Meng-Pei Lu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Apr. 12, 2022, as Appl. No. 17/718,461.
Application 17/718,461 is a continuation of application No. 16/908,942, filed on Jun. 23, 2020, granted, now 11,309,241.
Prior Publication US 2022/0238434 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76841 (2013.01); H01L 21/76877 (2013.01); H01L 23/53204 (2013.01)] 20 Claims
OG exemplary drawing
 
17. A method comprising:
forming an interconnect wire over a substrate;
forming a protection liner on outer surfaces of the interconnect wire;
forming a first interconnect dielectric layer around the interconnect wire;
forming a first etch stop layer selectively on the first interconnect dielectric layer and not on the protection liner; and
forming an interconnect via contacting an upper surface of the protection liner and coupled to the interconnect wire through the protection liner.