US 11,908,751 B2
Transistor isolation regions and methods of forming the same
Szu-Ying Chen, Hsinchu (TW); Sen-Hong Syue, Zhubei (TW); Huicheng Chang, Tainan (TW); and Yee-Chia Yeo, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 26, 2021, as Appl. No. 17/385,561.
Claims priority of provisional application 63/184,575, filed on May 5, 2021.
Prior Publication US 2022/0359311 A1, Nov. 10, 2022
Int. Cl. H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01)
CPC H01L 21/823878 (2013.01) [H01L 21/0228 (2013.01); H01L 21/76224 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
etching a trench in a substrate;
depositing a liner material in the trench with an atomic layer deposition process;
depositing a flowable material on the liner material and in the trench with a contouring flowable chemical vapor deposition process;
converting the liner material and the flowable material to a solid insulation material, a portion of the trench remaining unfilled by the solid insulation material;
forming a hybrid fin in the portion of the trench unfilled by the solid insulation materials; and
recessing the solid insulation material so that the hybrid fin protrudes above the solid insulation material.