US 11,908,746 B2
Semiconductor devices and methods of manufacturing thereof
Kuei-Yu Kao, Hsinchu (TW); Chao-Cheng Chen, Hsinchu (TW); Chih-Han Lin, Hsinchu (TW); Chen-Ping Chen, Toucheng Township (TW); Ming-Ching Chang, Hsinchu (TW); Shih-Yao Lin, New Taipei (TW); and Chih-Chung Chiu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 28, 2021, as Appl. No. 17/460,213.
Prior Publication US 2023/0061815 A1, Mar. 2, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01)
CPC H01L 21/823468 (2013.01) [H01L 21/823431 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of semiconductor layers vertically separated from one another;
a gate structure that comprises a lower portion and an upper portion, wherein the lower portion wraps around each of the plurality of semiconductor layers;
an etch stop layer; and
a gate spacer that extends along a sidewall of the upper portion of the gate structure and has a bottom surface;
wherein a portion of the bottom surface of the gate spacer and a top surface of a topmost one of the plurality of semiconductor layers form an angle that is less than 90 degrees; and
wherein the etch stop layer extends between the portion of the bottom surface of the gate spacer and the top surface of the topmost semiconductor layer.