US 11,908,702 B2
Gate structures in semiconductor devices
Hsiang-Pi Chang, New Taipei (TW); Chung-Liang Cheng, Changhua County (TW); I-Ming Chang, Shinchu (TW); Yao-Sheng Huang, Kaohsiung (TW); and Huang-Lin Chao, Hillsboro, OR (US)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 19, 2021, as Appl. No. 17/406,874.
Prior Publication US 2023/0058221 A1, Feb. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/3115 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/477 (2006.01); H01L 21/02 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 29/51 (2006.01); H01L 27/092 (2006.01)
CPC H01L 21/3115 (2013.01) [H01L 21/02192 (2013.01); H01L 21/477 (2013.01); H01L 21/823431 (2013.01); H01L 21/823857 (2013.01); H01L 27/0924 (2013.01); H01L 29/517 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a fin structure on a substrate;
forming a gate opening on the fin structure;
forming a metallic oxide layer within the gate opening;
forming a first dielectric layer on the metallic oxide layer, wherein the forming the first dielectric layer comprises depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer;
forming a second dielectric layer on the first dielectric layer;
forming a work function metal (WFM) layer on the second dielectric layer; and
forming a gate metal fill layer on the WFM layer.