US 11,908,543 B2
Latch circuit, transmission circuit including latch circuit, and semiconductor apparatus including transmission circuit
Eun Ji Choi, Icheon-si (KR); Keun Seon Ahn, Icheon-si (KR); Kwan Su Shon, Icheon-si (KR); and Yo Han Jeong, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 24, 2022, as Appl. No. 17/703,646.
Claims priority of application No. 10-2021-0133018 (KR), filed on Oct. 7, 2021.
Prior Publication US 2023/0111807 A1, Apr. 13, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01); H03K 3/037 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/106 (2013.01) [G11C 7/1087 (2013.01); G11C 7/222 (2013.01); H03K 3/037 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A latch circuit comprising:
a first detection unit configured to generate an output signal by detecting a level of an input terminal in response to a transition of a control clock signal during a normal read operation; and
a second detection unit configured to generate the output signal by detecting the level of the input terminal in response to the control clock signal during a state information read operation,
wherein the control clock signal transits repeatedly during the normal read operation, and the control clock signal is fixed to a first logic level during the state information read operation.