US 11,908,537 B2
Memory circuit architecture
David Li, San Diego, CA (US); Rahul Biradar, Kalaburgi (IN); Biju Manakkam Veetil, Bengaluru (IN); Po-Hung Chen, Los Angeles, CA (US); Ayan Paul, San Diego, CA (US); Sung Son, San Jose, CA (US); Shivendra Kushwaha, Bangalore (IN); Ravindra Reddy Chekkera, Vemula (IN); and Derek Yang, Poway, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 1, 2023, as Appl. No. 18/163,146.
Application 18/163,146 is a continuation of application No. 17/136,616, filed on Dec. 29, 2020, granted, now 11,600,307.
Prior Publication US 2023/0178118 A1, Jun. 8, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 5/02 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01)
CPC G11C 5/025 (2013.01) [G11C 7/06 (2013.01); G11C 7/1069 (2013.01); G11C 7/1096 (2013.01); G11C 8/08 (2013.01); G11C 8/10 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component;
wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit;
wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits, wherein there is a first axis between the first quadrant and the second quadrant about which the first set of input output circuits and the second set of input output circuits are symmetrical; and
wherein a third quadrant of the plurality of quadrants includes a third bit cell core and a third set of input output circuits, the third quadrant being symmetrical with the first quadrant along a second axis that is perpendicular to a direction of wordlines in the first bit cell core.