US 11,907,753 B2
Controller with caching and non-caching modes
Abhijeet Ashok Chachad, Plano, TX (US); Timothy David Anderson, University City, TX (US); and David Matthew Thompson, Dallas, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Nov. 7, 2022, as Appl. No. 17/981,591.
Application 17/981,591 is a continuation of application No. 16/882,329, filed on May 22, 2020, granted, now 11,494,224.
Claims priority of provisional application 62/852,461, filed on May 24, 2019.
Prior Publication US 2023/0058689 A1, Feb. 23, 2023
Int. Cl. G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 9/448 (2018.01); G06F 11/30 (2006.01); G06F 9/54 (2006.01); G06F 12/0811 (2016.01); G06F 9/38 (2018.01); G06F 12/0813 (2016.01); G06F 12/0817 (2016.01); G06F 9/30 (2018.01); G06F 12/0871 (2016.01); G06F 12/0891 (2016.01); G06F 12/12 (2016.01); G06F 13/16 (2006.01); G06F 12/0888 (2016.01); G06F 12/0831 (2016.01); G06F 12/0855 (2016.01); G06F 12/0804 (2016.01); G06F 12/121 (2016.01)
CPC G06F 9/467 (2013.01) [G06F 9/30047 (2013.01); G06F 9/30079 (2013.01); G06F 9/30098 (2013.01); G06F 9/30101 (2013.01); G06F 9/30189 (2013.01); G06F 9/3867 (2013.01); G06F 9/4498 (2018.02); G06F 9/4881 (2013.01); G06F 9/544 (2013.01); G06F 11/3037 (2013.01); G06F 12/0811 (2013.01); G06F 12/0813 (2013.01); G06F 12/0824 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/0855 (2013.01); G06F 12/0871 (2013.01); G06F 12/0888 (2013.01); G06F 12/0891 (2013.01); G06F 12/12 (2013.01); G06F 13/1668 (2013.01); G06F 12/0804 (2013.01); G06F 12/121 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/621 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first cache memory configured to store a set of entries;
a cache controller coupled to the first cache memory;
a second cache memory coupled to the cache controller, wherein:
the second cache memory has a set of address regions that includes a first address region that is associated with the set of entries; and
the second cache memory is configured to store a set of data in the first address region; and
a configuration register coupled to the cache controller and configured to store a set of configuration values that includes a respective configuration value for each address region of the set of address regions, wherein a first configuration value of the set of configuration values is associated with the first address region;
wherein the cache controller is configured to:
receive a read request associated with the set of data;
retrieve the set of data from the second cache memory;
provide the set of data;
determine whether to store the set of data in the first cache memory based on the first configuration value;
determine a change in the first configuration value such that the first configuration value indicates not to store entries associated with the first address region in the first cache memory; and
based on the change, evict the set of entries from the first cache memory.