CPC G06F 9/30101 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/556 (2013.01); G06F 9/30105 (2013.01); G06F 30/34 (2020.01); G06F 30/343 (2020.01); G06F 30/38 (2020.01); G06N 20/00 (2019.01); H03K 19/177 (2013.01); H03K 19/17748 (2013.01); H03M 7/24 (2013.01); G06F 7/483 (2013.01)] | 20 Claims |
1. A digital signal processing (DSP) block comprising:
a plurality of columns of weight registers;
a plurality of inputs configurable to receive a first plurality of values and a second plurality of values, wherein the first plurality of values is stored in the plurality of columns of weight registers after being received;
conversion circuitry configurable to receive a shared exponent for the second plurality of values and convert fixed-point values to floating-point values based on the shared exponent; and
a plurality of multipliers configurable to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.
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