US 11,907,719 B2
FPGA specialist processing block for machine learning
Martin Langhammer, Alderbury (GB); Dongdong Chen, San Jose, CA (US); and Jason R. Bergendahl, Cupertino, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 26, 2020, as Appl. No. 16/914,009.
Claims priority of provisional application 62/948,110, filed on Dec. 13, 2019.
Claims priority of provisional application 62/948,114, filed on Dec. 13, 2019.
Claims priority of provisional application 62/948,124, filed on Dec. 13, 2019.
Prior Publication US 2020/0327271 A1, Oct. 15, 2020
Int. Cl. G06F 9/30 (2018.01); G06N 20/00 (2019.01); G06F 30/343 (2020.01); G06F 30/34 (2020.01); G06F 30/38 (2020.01); G06F 7/50 (2006.01); G06F 7/523 (2006.01); H03K 19/17748 (2020.01); H03M 7/24 (2006.01); G06F 7/556 (2006.01); H03K 19/177 (2020.01); G06F 7/483 (2006.01)
CPC G06F 9/30101 (2013.01) [G06F 7/50 (2013.01); G06F 7/523 (2013.01); G06F 7/556 (2013.01); G06F 9/30105 (2013.01); G06F 30/34 (2020.01); G06F 30/343 (2020.01); G06F 30/38 (2020.01); G06N 20/00 (2019.01); H03K 19/177 (2013.01); H03K 19/17748 (2013.01); H03M 7/24 (2013.01); G06F 7/483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A digital signal processing (DSP) block comprising:
a plurality of columns of weight registers;
a plurality of inputs configurable to receive a first plurality of values and a second plurality of values, wherein the first plurality of values is stored in the plurality of columns of weight registers after being received;
conversion circuitry configurable to receive a shared exponent for the second plurality of values and convert fixed-point values to floating-point values based on the shared exponent; and
a plurality of multipliers configurable to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.