CPC G06F 30/398 (2020.01) [G03F 1/36 (2013.01); G03F 1/70 (2013.01); G06F 30/20 (2020.01)] | 20 Claims |
1. A method of generating an integrated circuit (IC) layout diagram, the method comprising:
receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region;
determining a second gate resistance value based on the location and the width;
using the first and second resistance values by performing an alternating current (AC) simulation based on the IC layout diagram to determine that the IC layout diagram does not comply with a design specification; and
based on the non-compliance with the design specification, modifying the IC layout diagram.
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