CPC G06F 30/33 (2020.01) [G06F 30/323 (2020.01); G06F 30/333 (2020.01)] | 10 Claims |
1. A computing system configured to verify design of an integrated circuit, the computing system comprising:
a memory configured to store computer executable instructions; and
a processor configured to generate a first coverage model for at least two high-level parameters from the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard or hardware description language code by executing the computer executable instructions, generate a second coverage model for low-level internal signals from the hardware description language code by executing the computer executable instructions, and generate a plurality of test packets for a regression test by using at least one of the first coverage model or the second coverage model by executing the computer executable instructions.
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