US 11,907,629 B2
Computing system and method of verifying circuit design in computing system
Soonwoo Choi, Seoul (KR); Jung Woon Lee, Daejeon (KR); and Junyoung Jeong, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 16, 2021, as Appl. No. 17/552,819.
Claims priority of application No. 10-2021-0009592 (KR), filed on Jan. 22, 2021; and application No. 10-2021-0064979 (KR), filed on May 20, 2021.
Prior Publication US 2022/0237351 A1, Jul. 28, 2022
Int. Cl. G06F 30/33 (2020.01); G06F 30/323 (2020.01); G06F 30/333 (2020.01)
CPC G06F 30/33 (2020.01) [G06F 30/323 (2020.01); G06F 30/333 (2020.01)] 10 Claims
OG exemplary drawing
 
1. A computing system configured to verify design of an integrated circuit, the computing system comprising:
a memory configured to store computer executable instructions; and
a processor configured to generate a first coverage model for at least two high-level parameters from the Institute of Electrical and Electronics Engineers (IEEE) 802.11 standard or hardware description language code by executing the computer executable instructions, generate a second coverage model for low-level internal signals from the hardware description language code by executing the computer executable instructions, and generate a plurality of test packets for a regression test by using at least one of the first coverage model or the second coverage model by executing the computer executable instructions.