US 11,907,580 B2
Corrective read of a memory device with reduced latency
Tao Liu, San Jose, CA (US); Zhengang Chen, San Jose, CA (US); and Ting Luo, Santa Clara, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 22, 2021, as Appl. No. 17/645,683.
Prior Publication US 2023/0195381 A1, Jun. 22, 2023
Int. Cl. G06F 3/06 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0679 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G06F 2212/7206 (2013.01); G11C 16/0483 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory device; and
a controller coupled with the memory device and configured to cause the apparatus to:
identify a read error based at least in part on receiving, from the memory device, first information that is associated with a first read operation of the memory device;
select a trim setting from a plurality of trim settings based at least in part on identifying a data retention condition associated with the first information;
transmit, to the memory device, an indication to initiate a second read operation of the memory device in accordance with the selected trim setting; and
perform a decoding operation based at least in part on receiving, from the memory device, second information that is associated with the second read operation of the memory device.