US 11,907,545 B2
On-the-fly multiplexing scheme for compressed soft bit data in non-volatile memories
YenLung Li, San Jose, CA (US); Siddarth Naga Murty Bassa, San Jose, CA (US); Chen Chen, Mountain View, CA (US); and Hua-Ling Cynthia Hsu, Fremont, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Apr. 28, 2022, as Appl. No. 17/731,971.
Application 17/731,971 is a continuation in part of application No. 17/666,657, filed on Feb. 8, 2022.
Application 17/666,657 is a continuation in part of application No. 17/557,236, filed on Dec. 21, 2021.
Claims priority of provisional application 63/244,951, filed on Sep. 16, 2021.
Prior Publication US 2023/0095127 A1, Mar. 30, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0619 (2013.01) [G06F 3/0617 (2013.01); G06F 3/0656 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A non-volatile memory device, comprising:
a control circuit configured to connect to a plurality of columns, each column comprising one or more bit lines each connected to a corresponding plurality of memory cells, the plurality of columns including a plurality of regular columns and one or more spare columns, the control circuit comprising:
a plurality of sense amplifiers each configured to read data from the memory cells connected to a corresponding one or more bit lines of the plurality of columns;
a plurality of sets of internal data latches, each set of internal data latches configured to store data associated with a corresponding one of the sense amplifiers; and
an input-output interface, including a plurality of data buffers, configured to provide data to an external data bus,
the control circuit configured to:
perform a read operation by each of the sense amplifiers on a plurality of memory cells;
store results of the read operation by each of the sense amplifiers in the corresponding set of internal data latches;
compress the results of the read operation by each of the sense amplifiers within the corresponding set of internal data latches;
transfer the compressed results of the read operation to the input-output interface;
re-order bits of the compressed results of the read operation;
subsequent to re-ordering the compressed results of the read operation, replace the compressed results of the read operation from defective ones of the regular columns with corresponding compressed results of the read operation from spare columns within the input-output interface by multiplexing the re-ordered bits of the compressed results of the read operation;
store the re-ordered bits of the compressed results with the compressed results of the read operation from defective ones of the regular columns replaced with corresponding compressed results of the read operation from spare columns in the plurality of data buffers; and
transfer the compressed results of the read operation, including replaced compressed results of the read operation, from the plurality of data buffers to the external data bus.