US 11,907,528 B2
Multi-processor bridge with cache allocate awareness
Kai Chirca, Dallas, TX (US); Daniel Wu, Plano, TX (US); and Matthew David Pierson, Frisco, TX (US)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Jul. 20, 2021, as Appl. No. 17/380,297.
Application 17/380,297 is a continuation of application No. 16/601,913, filed on Oct. 15, 2019, granted, now 11,099,993.
Claims priority of provisional application 62/745,842, filed on Oct. 15, 2018.
Prior Publication US 2021/0349821 A1, Nov. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/0811 (2016.01); G06F 12/0815 (2016.01); G06F 12/0855 (2016.01); G06F 13/16 (2006.01); G06F 12/0875 (2016.01); G06F 12/084 (2016.01); G06F 13/40 (2006.01); G06F 12/06 (2006.01); G06F 9/30 (2018.01); H03M 13/01 (2006.01); H03M 13/09 (2006.01); H03M 13/15 (2006.01); H03M 13/27 (2006.01); G06F 12/1009 (2016.01); G06F 12/10 (2016.01); G06F 12/0817 (2016.01); G06F 12/0831 (2016.01); G06F 13/12 (2006.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 12/0891 (2016.01); G06F 12/0846 (2016.01); G06F 12/0862 (2016.01)
CPC G06F 3/0604 (2013.01) [G06F 3/064 (2013.01); G06F 3/0607 (2013.01); G06F 3/0632 (2013.01); G06F 3/0658 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 3/0679 (2013.01); G06F 9/30101 (2013.01); G06F 9/30123 (2013.01); G06F 9/3897 (2013.01); G06F 9/4881 (2013.01); G06F 9/5016 (2013.01); G06F 12/0607 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/0828 (2013.01); G06F 12/0831 (2013.01); G06F 12/0855 (2013.01); G06F 12/0857 (2013.01); G06F 12/0875 (2013.01); G06F 12/0891 (2013.01); G06F 12/10 (2013.01); G06F 12/1009 (2013.01); G06F 13/124 (2013.01); G06F 13/1642 (2013.01); G06F 13/1663 (2013.01); G06F 13/1668 (2013.01); G06F 13/4027 (2013.01); H03M 13/015 (2013.01); H03M 13/098 (2013.01); H03M 13/1575 (2013.01); H03M 13/276 (2013.01); H03M 13/2785 (2013.01); G06F 12/0833 (2013.01); G06F 12/0846 (2013.01); G06F 12/0851 (2013.01); G06F 12/0862 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/1048 (2013.01); G06F 2212/304 (2013.01); G06F 2212/452 (2013.01); G06F 2212/6024 (2013.01); G06F 2212/657 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A processing system comprising:
a plurality of processors including a first processor;
a cache memory coupled to the plurality of processors; and
a shared memory controller comprising:
circuitry configured to receive a memory management command having a specification to perform a memory management operation to load data into a memory location of the cache memory before the first processor executes an input/output instruction that requests the data from the memory location;
formatting circuitry configured to format the memory management command into a formatted command; and
routing circuitry configured to route the formatted command based on the specification; and
response circuitry configured to receive a response indicating the data was loaded into the memory location.