US 11,907,157 B2
Reconfigurable processor circuit architecture
Paul L. Master, Sunnyvale, CA (US); Steven K. Knapp, Soquel, CA (US); Raymond J. Andraka, North Kings Town, RI (US); Alexei Beliaev, Campbell, CA (US); Martin A. Franz, Sunnyvale, CA (US); Rene Meessen, San Francisco, CA (US); and Frederick Curtis Furtek, Menlo Park, CA (US)
Assigned to Cornami, Inc., Campbell, CA (US)
Filed by Cornami, Inc., Dallas, TX (US)
Filed on Dec. 31, 2022, as Appl. No. 18/092,247.
Application 18/092,247 is a continuation of application No. 17/967,173, filed on Oct. 17, 2022.
Application 17/967,173 is a continuation of application No. 17/015,973, filed on Sep. 9, 2020, granted, now 11,494,331, issued on Nov. 8, 2022.
Claims priority of provisional application 62/899,025, filed on Sep. 11, 2019.
Claims priority of provisional application 62/898,452, filed on Sep. 10, 2019.
Prior Publication US 2023/0153265 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 21/44 (2013.01); G06F 15/78 (2006.01); G06F 15/80 (2006.01); G06F 7/523 (2006.01); G06F 7/50 (2006.01); H03K 19/21 (2006.01); G06F 9/48 (2006.01); G06F 9/54 (2006.01); G06F 5/01 (2006.01); G06F 9/30 (2018.01); G06F 7/487 (2006.01); G06F 7/52 (2006.01); G06F 7/544 (2006.01); G06F 9/38 (2018.01)
CPC G06F 15/80 (2013.01) [G06F 5/01 (2013.01); G06F 7/487 (2013.01); G06F 7/50 (2013.01); G06F 7/52 (2013.01); G06F 7/523 (2013.01); G06F 7/5443 (2013.01); G06F 9/30098 (2013.01); G06F 9/3856 (2023.08); G06F 9/4881 (2013.01); G06F 9/54 (2013.01); H03K 19/21 (2013.01); G06F 2207/382 (2013.01)] 32 Claims
OG exemplary drawing
 
1. A reconfigurable processor circuit comprising:
a first interconnection network;
a second interconnection network;
a processor coupled to the first interconnection network; and
a plurality of computational cores arranged in an array, the plurality of computational cores coupled to the first interconnection network and to the second interconnection network, the second interconnection network coupling adjacent computational cores of the plurality of computational cores, each computational core comprising:
a memory circuit;
a reconfigurable arithmetic circuit comprising:
at least one input reordering queue;
a configurable multiplier coupled to the at least one input reordering queue;
a configurable shifter and combiner network coupled to configurable multiplier; and
an accumulator circuit coupled to the configurable shifter and combiner network;
and
a zeros compression circuit comprising:
a zeros counter configured to count one or more sequential data packets having a zero data payload to generate a zeros count; and
a first data packet generator configured, when a next data packet has a nonzero data payload, to encode the zeros count as a suffix in the next data packet.