US 11,907,152 B2
Reconfigurable server and server rack with same
Augusto Panella, Naperville, IL (US); Allan Cantle, Westlake Village, CA (US); Ray Matyka, Plainfield, IL (US); and John W. Comish, Jr., Acton, CA (US)
Assigned to Molex, LLC, Lisle, IL (US)
Filed by Molex, LLC, Lisle, IL (US)
Filed on Nov. 18, 2022, as Appl. No. 17/989,694.
Application 17/989,694 is a continuation of application No. 17/392,291, filed on Aug. 3, 2021, granted, now 11,513,990.
Application 17/392,291 is a continuation of application No. 16/610,922, granted, now 11,100,026, issued on Aug. 24, 2021, previously published as PCT/US2018/032652, filed on May 15, 2018.
Claims priority of provisional application 62/506,374, filed on May 15, 2017.
Prior Publication US 2023/0079644 A1, Mar. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/40 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); H04Q 1/04 (2006.01); G06F 13/38 (2006.01)
CPC G06F 13/4027 (2013.01) [G06F 13/1668 (2013.01); G06F 13/385 (2013.01); G06F 13/4068 (2013.01); G06F 13/423 (2013.01); G06F 13/4243 (2013.01); G06F 13/4282 (2013.01); H04Q 1/04 (2013.01); G06F 2213/0026 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A reconfigurable server, comprising:
main memory;
a processor module with a processor array, the processor array connected to the main memory and having a plurality of peripheral interconnect channels supporting a first communication protocol that is serial and a plurality of high data rate capable channels supporting a second communication protocol different than the first communication protocol;
a near-memory accelerator module connected to one of the high data rate capable channels, the near-memory accelerator module having a programmable logic device (PLD) that is a field programmable gate array (FPGA), wherein the PLD is connected to one of the high data rate capable channels and the PLD is connected to a peripheral interconnect switch with a predetermined number of interconnect lanes, the peripheral interconnect switch connected to a near-memory module with the predetermined number of interconnect lanes,
wherein a bandwidth between the PLD and the near-memory module is only within ten percent of a bandwidth between the PLD and the processor array.