CPC G06F 13/4027 (2013.01) [G06F 13/1668 (2013.01); G06F 13/385 (2013.01); G06F 13/4068 (2013.01); G06F 13/423 (2013.01); G06F 13/4243 (2013.01); G06F 13/4282 (2013.01); H04Q 1/04 (2013.01); G06F 2213/0026 (2013.01)] | 20 Claims |
1. A reconfigurable server, comprising:
main memory;
a processor module with a processor array, the processor array connected to the main memory and having a plurality of peripheral interconnect channels supporting a first communication protocol that is serial and a plurality of high data rate capable channels supporting a second communication protocol different than the first communication protocol;
a near-memory accelerator module connected to one of the high data rate capable channels, the near-memory accelerator module having a programmable logic device (PLD) that is a field programmable gate array (FPGA), wherein the PLD is connected to one of the high data rate capable channels and the PLD is connected to a peripheral interconnect switch with a predetermined number of interconnect lanes, the peripheral interconnect switch connected to a near-memory module with the predetermined number of interconnect lanes,
wherein a bandwidth between the PLD and the near-memory module is only within ten percent of a bandwidth between the PLD and the processor array.
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