US 11,907,134 B1
Nonvolatile memory controller supporting variable configurability and forward compatibility
Robert Lercari, Thousand Oaks, CA (US); Alan Chen, Simi Valley, CA (US); Mike Jadon, Manhattan Beach, CA (US); Craig Robertson, Simi Valley, CA (US); and Andrey V. Kuzmin, Moscow (RU)
Assigned to Radian Memory Systems, Inc., Manhattan Beach, CA (US)
Filed by Radian Memory Systems, Inc., Manhattan Beach, CA (US)
Filed on Sep. 8, 2021, as Appl. No. 17/469,758.
Application 17/469,758 is a division of application No. 16/808,304, filed on Mar. 3, 2020, granted, now 11,221,959.
Application 16/808,304 is a continuation of application No. 15/690,006, filed on Aug. 29, 2017, granted, now 10,642,748, issued on May 5, 2020.
Application 15/690,006 is a continuation of application No. 15/074,778, filed on Mar. 18, 2016, granted, now 9,785,572, issued on Oct. 10, 2017.
Application 15/074,778 is a continuation of application No. 14/880,529, filed on Oct. 12, 2015, granted, now 9,542,118, issued on Jan. 10, 2017.
Application 14/880,529 is a continuation in part of application No. 14/848,273, filed on Sep. 8, 2015, granted, now 10,642,505, issued on May 5, 2020.
Claims priority of provisional application 62/199,969, filed on Jul. 31, 2015.
Claims priority of provisional application 62/194,172, filed on Jul. 17, 2015.
Claims priority of provisional application 62/063,357, filed on Oct. 13, 2014.
Claims priority of provisional application 62/048,162, filed on Sep. 9, 2014.
Int. Cl. G06F 12/1009 (2016.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 12/109 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 3/064 (2013.01); G06F 3/0616 (2013.01); G06F 3/0688 (2013.01); G06F 12/0246 (2013.01); G06F 12/109 (2013.01); G06F 3/0659 (2013.01); G06F 3/0662 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7202 (2013.01); G06F 2212/7205 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory controller to control nonvolatile memory, the memory controller comprising:
circuitry to map host-provided addresses to physical addresses in the nonvolatile memory according to one of two alternate mappings; and
a register to store a programmably-defined address mapping parameter;
wherein the circuitry is to map data, received with sequentially-received write requests, to a number of respective storage units of a type of storage unit, wherein the type is a same one from a group of channels, dies, erase units, planes, and pages, wherein the number of the respective storage units of the type is variable dependent on a value of the programmably-defined address mapping parameter;
wherein each host-provided address comprises a first portion and a second portion, and
for a first one of the two alternate mappings, the first portion of each host-provided address is mapped to a first number of first storage units of the nonvolatile memory and the second portion of each host-provided address is mapped to a first number of second storage units of the nonvolatile memory,
for a second one of the two alternate mappings, the first portion of each host-provided address is mapped by said circuitry to a second number of the first storage units and the second portion of each host-provided address is mapped by said circuitry to a second number of the second storage units;
the first storage units are respective units of a first type of units from the group, and the second storage units are respective units of a second type of units from the group, and
one of the first portion and the second portion can be mapped to a non-power of two set of structural addresses and the circuitry to map is to perform modulo arithmetic on each host-provided address to recover the other of the first portion and the second portion, with no address in a range of addresses represented by the first portion and the second portion remaining unmapped to a storage location in the nonvolatile memory; and
circuitry to service the write requests by issuing commands accompanied by the physical addresses, the physical addresses being generated using the one of the two alternate mappings.