| CPC G06F 1/08 (2013.01) [G06F 1/10 (2013.01); H03K 19/20 (2013.01)] | 19 Claims |
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1. A multi-core system comprising:
a multi-core processor including a plurality of processor cores configured to operate based on a plurality of core clock signals, respectively;
a function block configured to communicate with the multi-core processor based on an interface clock signal;
a clock management circuit configured to:
generate each of the plurality of core clock signals by selecting one of a first clock signal having a first frequency and a second clock signal having a second frequency different from the first frequency based on each of a plurality of frequency selection signals,
generate the interface clock signal based on the second clock signal,
fix a frequency of the interface signal to the second frequency regardless of the plurality of frequency selection signals, and
change a frequency of each of the plurality of core deck signals between the frequency and the second frequency based on each of the plurality of frequency selection signals; and
a control circuit configured to generate the plurality of frequency selection signals corresponding to the plurality of processor cores, respectively.
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