US 11,906,864 B2
Dual-gate array substrate and display device
Pengcheng Zang, Beijing (CN); Weiyun Huang, Beijing (CN); Xiaojing Qi, Beijing (CN); and Tingliang Liu, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Chengdu (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Chengdu (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Aug. 10, 2022, as Appl. No. 17/884,708.
Application 17/884,708 is a continuation in part of application No. 16/656,969, filed on Oct. 18, 2019, granted, now 11,442,318.
Application 16/656,969 is a continuation in part of application No. 15/519,596, granted, now 10,488,718, issued on Nov. 26, 2019, previously published as PCT/CN2016/081109, filed on May 5, 2016.
Claims priority of application No. 201610074047.1 (CN), filed on Feb. 2, 2016.
Prior Publication US 2023/0037033 A1, Feb. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G02F 1/1362 (2006.01); H01L 27/12 (2006.01); G02F 1/136 (2006.01); G02F 1/1343 (2006.01); G02F 1/1368 (2006.01)
CPC G02F 1/136295 (2021.01) [G02F 1/13606 (2021.01); G02F 1/134318 (2021.01); G02F 1/134363 (2013.01); H01L 27/124 (2013.01); G02F 1/1368 (2013.01); G02F 1/134336 (2013.01); G02F 2201/40 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A dual-gate array substrate, comprising:
a plurality of gate lines arranged in a first direction, each of the gate lines being extended in a second direction that is perpendicular to the first direction;
a plurality of primary signal lines and secondary signal lines arranged alternately in the second direction and extended in the first direction; and
a plurality of pixel units each enclosed and defined by jointing adjacent two of the gate lines insulative with corresponding ones of the primary signal lines or the secondary signal lines, the pixel units each including pixel electrodes, the primary signal lines being connected to a drive unit and being connected respectively to ones of the pixel units that are adjacent thereto;
wherein the dual-gate array substrate further comprises common electrodes located in a different layer from the pixel units and comprising a plurality of main electrodes and a plurality of branching electrodes;
wherein the secondary signal lines are connected to the common electrodes;
wherein an orthographic projection of one of the main electrodes on the dual-gate array substrate at least covers a corresponding one of the primary signal lines and does not overlap orthographic projections of two pixel electrodes, adjacent to the corresponding one of the primary signal lines, of the pixel electrodes on the dual-gate array substrate;
wherein each gate line comprises a protrusion protruded in the first direction; and
wherein a line width of each of the secondary signal lines is not greater than a line width of each of the primary signal lines.