US 12,232,434 B2
Multi-doped data storage structure configured to improve resistive memory cell performance
Bi-Shen Lee, Hsin-Chu (TW); Hai-Dang Trinh, Hsinchu (TW); Fa-Shen Jiang, Taoyuan (TW); and Hsun-Chung Kuang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jun. 30, 2022, as Appl. No. 17/854,982.
Application 17/854,982 is a division of application No. 16/940,529, filed on Jul. 28, 2020, granted, now 11,404,638.
Prior Publication US 2022/0336737 A1, Oct. 20, 2022
Int. Cl. H10N 70/00 (2023.01); G11C 13/00 (2006.01)
CPC H10N 70/8265 (2023.02) [G11C 13/0007 (2013.01); H10N 70/841 (2023.02); H10N 70/8833 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for forming an integrated chip, the method comprising:
forming a bottom electrode over a substrate;
forming a data storage structure on the bottom electrode, wherein the data storage structure comprises a switching layer and a doped switching layer contacting the switching layer, wherein the doped switching layer comprises a first dopant with a first atomic percent and a second dopant with a second atomic percent, wherein the first atomic percent is different from the second atomic percent; and
forming a top electrode on the data storage structure.