US 12,232,432 B2
Memory cells with sidewall and bulk regions in vertical structures
Lorenzo Fratin, Buccinasco (IT); Enrico Varesi, Milan (IT); and Paolo Fantini, Vimercate (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 26, 2024, as Appl. No. 18/617,007.
Application 18/617,007 is a division of application No. 17/332,672, filed on May 27, 2021, granted, now 11,957,068.
Prior Publication US 2024/0315150 A1, Sep. 19, 2024
Int. Cl. H10N 70/20 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/231 (2023.02) [H10B 63/84 (2023.02); H10N 70/041 (2023.02); H10N 70/063 (2023.02); H10N 70/066 (2023.02); H10N 70/882 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a substrate;
forming a stack of alternating layers on the substrate, the stack of alternating layers comprising conductive materials and dielectric materials;
etching the stack of alternating layers to form a plurality of cavities;
depositing a chalcogenide material into a cavity of the plurality of cavities to form a self-selecting storage element that is in contact with a first conductive material of the conductive materials and two dielectric materials of the dielectric materials and that comprises a bulk region and a sidewall region, the bulk region extending between the first conductive material and the sidewall region and comprising at least a first portion of the chalcogenide material having a first composition, and the sidewall region extending from the bulk region and comprising at least a second portion of the chalcogenide material having a second composition that is different than the first composition; and
depositing a second conductive material that contacts the sidewall region of the chalcogenide material.