US 12,232,431 B2
Memory device
Kunifumi Suzuki, Yokkaichi Mie (JP); and Yuuichi Kamimuta, Yokkaichi Mie (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jan. 28, 2022, as Appl. No. 17/587,267.
Claims priority of application No. 2021-097862 (JP), filed on Jun. 11, 2021.
Prior Publication US 2022/0399488 A1, Dec. 15, 2022
Int. Cl. H10N 70/20 (2023.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01)
CPC H10N 70/231 (2023.02) [H10B 63/24 (2023.02); H10B 63/84 (2023.02); H10N 70/063 (2023.02); H10N 70/8828 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first interconnect layer;
a second interconnect layer;
a phase-change layer between the first interconnect layer and the second interconnect layer and configured to reversibly transition between a crystalline state and an amorphous state; and
an adjacent layer contacting and embedded in the phase-change layer and comprising tellurium and at least one of titanium, zirconium, or hafnium.