| CPC H10N 70/231 (2023.02) [G11C 13/0004 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); H10B 12/50 (2023.02); H10N 70/841 (2023.02); H10B 12/01 (2023.02); H10N 70/883 (2023.02)] | 16 Claims |

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1. A phase-change memory device comprising:
a first electrode;
a second electrode; and
a phase-change memory cell interposed between the first electrode and the second electrode,
wherein the phase-change memory cell comprises:
a P-type intermediate layer used as data storage as a crystal state changes due to a voltage applied through the first electrode and the second electrode;
an upper layer and a lower layer formed using an N-type semiconductor material at both ends of the intermediate layer; and
at least one tunneling thin film arranged in at least one area from among an area between the upper layer and the intermediate layer and an area between the lower layer and the intermediate layer, the at least one tunneling thin film being configured to reduce a leakage current in the intermediate layer or prevent intermixing between a P-type dopant and an N-type dopant.
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