US 12,232,407 B2
Display device and method of fabricating the same
Won-Kyu Kwak, Yongin-si (KR); Hwan-Soo Jang, Yongin-si (KR); and Jae-Yong Lee, Yongin-si (KR)
Assigned to SAMSUNG DISPLAY CO., LTD., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Dec. 4, 2023, as Appl. No. 18/528,136.
Application 16/165,155 is a division of application No. 15/586,784, filed on May 4, 2017, granted, now 10,109,797, issued on Oct. 23, 2018.
Application 15/586,784 is a division of application No. 14/705,166, filed on May 6, 2015, granted, now 9,653,368, issued on May 16, 2017.
Application 18/528,136 is a continuation of application No. 17/741,730, filed on May 11, 2022, granted, now 11,864,454.
Application 17/741,730 is a continuation of application No. 16/600,042, filed on Oct. 11, 2019, granted, now 11,335,856, issued on May 17, 2022.
Application 16/600,042 is a continuation of application No. 16/165,155, filed on Oct. 19, 2018, granted, now 10,446,755, issued on Oct. 15, 2019.
Claims priority of application No. 10-2014-0101136 (KR), filed on Aug. 6, 2014.
Prior Publication US 2024/0107869 A1, Mar. 28, 2024
Int. Cl. H10K 71/70 (2023.01); G09G 3/00 (2006.01); G09G 3/3225 (2016.01); H01L 21/66 (2006.01); H01L 27/12 (2006.01); H10K 50/84 (2023.01); H10K 59/12 (2023.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01); H10K 71/50 (2023.01); H10K 77/10 (2023.01); H10K 102/00 (2023.01)
CPC H10K 71/70 (2023.02) [G09G 3/006 (2013.01); H01L 22/14 (2013.01); H01L 22/32 (2013.01); H01L 27/124 (2013.01); H01L 27/1259 (2013.01); H10K 50/84 (2023.02); H10K 59/131 (2023.02); H10K 71/00 (2023.02); H10K 71/50 (2023.02); H10K 77/111 (2023.02); G09G 3/3225 (2013.01); G09G 2330/12 (2013.01); H10K 59/1201 (2023.02); H10K 2102/311 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A display device, comprising:
a substrate including a display area and a non-display area, the display area including a plurality of pixels electrically connected to a plurality of data lines and to a plurality of scan lines;
a first pad to receive a signal, the first pad including a first test voltage pad and a second test voltage pad separated from each other;
at least one first transistor electrically connected between one of the plurality of data lines of the display area and the first pad;
at least one outline electrically connected between the at least one first transistor and the first pad, the at least one outline being disposed in a non-display area, wherein
the at least one outline comprises a first outline and a second outline separated from each other,
the first outline is electrically connected between a first data line of the plurality of data lines and the first test voltage pad,
the second outline is electrically connected between a third data line of the plurality of data lines and the second test voltage pad, and
the first and second outlines are positioned closest to an edge of the substrate.