US 12,232,382 B2
Display substrate and manufacturing method thereof, display device
Pengfei Yu, Beijing (CN); Lu Bai, Beijing (CN); Jie Dai, Beijing (CN); and Linhong Han, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Chengdu (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Dec. 11, 2023, as Appl. No. 18/535,236.
Application 18/535,236 is a continuation of application No. 17/434,256, granted, now 11,875,749, previously published as PCT/CN2020/084235, filed on Apr. 10, 2020.
Prior Publication US 2024/0112638 A1, Apr. 4, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/3266 (2016.01); G11C 19/28 (2006.01); H10K 59/131 (2023.01)
CPC H10K 59/131 (2023.02) [G09G 3/3266 (2013.01); G11C 19/28 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0286 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A display substrate, comprising:
a base substrate, comprising a display region and a peripheral region located at least a side of the display region, and a shift register unit and a first clock signal line that are on the peripheral region of the base substrate,
wherein the first clock signal line extends along a first direction on the base substrate and is connected to a first clock signal terminal to configure to provide a first clock signal to the shift register unit;
the shift register unit comprises an input circuit, an output circuit, a first control circuit and an output control circuit;
the input circuit is configured to input an input signal to a first node in response to the first clock signal;
the output circuit is configured to output an output signal to an output terminal;
the first control circuit is configured to control a level of a second node in response to a level of the first node and the first clock signal; and
the output control circuit is configured to control a level of the output terminal under control of a level of the second node,
the output control circuit comprises an output control transistor and a first capacitor, and
the output circuit comprises an output transistor and a second capacitor;
an active layer of the output control transistor and an active layer of the output transistor are integral and extend along the first direction,
the active layer of the output control transistor and the active layer of the output transistor comprises a first output semiconductor layer and a second output semiconductor layer which are arranged side by side in a second direction different from the first direction, an orthographic projection of the second output semiconductor layer on the base substrate is between an orthographic projection of the first output semiconductor layer on the base substrate and the display region,
an end of the orthographic projection of the first output semiconductor layer on the base substrate away from the display region comprises a first sub-notch,
an end of the orthographic projection of the second output semiconductor layer on the base substrate close to the display region comprises a second sub-notch.