US 12,232,368 B2
Display device and electronic device
Hideaki Shishido, Kanagawa (JP); and Naoto Kusumoto, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed on May 12, 2022, as Appl. No. 17/742,842.
Application 17/742,842 is a continuation of application No. 16/743,220, filed on Jan. 15, 2020, granted, now 11,335,746.
Application 16/743,220 is a continuation of application No. 15/654,108, filed on Jul. 19, 2017, granted, now 10,541,375, issued on Jan. 21, 2020.
Claims priority of application No. 2016-142898 (JP), filed on Jul. 21, 2016.
Prior Publication US 2022/0271109 A1, Aug. 25, 2022
Int. Cl. H10K 59/122 (2023.01); G02F 1/133 (2006.01); G06F 3/041 (2006.01); G09G 3/20 (2006.01); G09G 3/3225 (2016.01); G09G 3/3233 (2016.01); G09G 3/3258 (2016.01); G09G 3/36 (2006.01); H01L 29/786 (2006.01); H10K 10/84 (2023.01); H10K 50/814 (2023.01); H10K 59/121 (2023.01); H10K 59/128 (2023.01); H01L 27/12 (2006.01); H10K 50/115 (2023.01); H10K 71/20 (2023.01)
CPC H10K 59/122 (2023.02) [G02F 1/13306 (2013.01); G06F 3/0412 (2013.01); G09G 3/2092 (2013.01); G09G 3/3225 (2013.01); G09G 3/3233 (2013.01); G09G 3/3258 (2013.01); G09G 3/3648 (2013.01); H01L 29/7869 (2013.01); H10K 10/84 (2023.02); H10K 50/814 (2023.02); H10K 59/1213 (2023.02); H10K 59/128 (2023.02); G02F 2201/44 (2013.01); G02F 2203/02 (2013.01); G06F 3/041 (2013.01); G06F 2203/04103 (2013.01); G09G 2310/0291 (2013.01); H01L 27/1225 (2013.01); H10K 50/115 (2023.02); H10K 71/231 (2023.02)] 4 Claims
OG exemplary drawing
 
1. A display device comprising:
a pixel circuit and a driver circuit on a same plane as the pixel circuit,
wherein the driver circuit includes a selection circuit and a buffer circuit,
wherein the selection circuit includes a first transistor and the buffer circuit includes a second transistor,
wherein a channel width of the second transistor is larger than a channel width of the first transistor,
wherein an interlayer insulating film is provided over a channel formation region of the second transistor,
wherein a channel formation region of the first transistor is provided over the interlayer insulating film,
wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor through an opening provided in the interlayer insulating film,
wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to a power supply line,
wherein the other of the source and the drain electrode of the second transistor is electrically connected to a gate line of the pixel circuit,
wherein, in a plan view, the power supply line has a region extending in a first direction,
wherein, in the plan view, the gate line has a region extending in the first direction,
wherein, in the plan view, the one of the source electrode and the drain electrode of the first transistor has a region extending in the first direction,
wherein, in the plan view, the other of the source electrode and the drain electrode of the first transistor has a region extending in the first direction,
wherein, in the plan view, a gate electrode of the first transistor has a region extending in a second direction,
wherein, in the plan view, a channel length direction of the second transistor is arranged in the second direction, and
wherein, in the plan view, the gate electrode of the second transistor has a region extending in the first direction.