US 12,232,336 B2
Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same
Fa-Shen Jiang, Taoyuan (TW); Hsia-Wei Chen, Taipei (TW); Hai-Dang Trinh, Hsinchu (TW); and Hsun-Chung Kuang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Nov. 10, 2023, as Appl. No. 18/506,157.
Application 18/506,157 is a continuation of application No. 17/227,438, filed on Apr. 12, 2021, granted, now 11,856,801.
Claims priority of provisional application 63/039,534, filed on Jun. 16, 2020.
Prior Publication US 2024/0074217 A1, Feb. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); H10B 99/00 (2023.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01)
CPC H10B 99/00 (2023.02) [H10B 99/22 (2023.02); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a field effect transistor; and
a variable-capacitance capacitor, wherein:
the field effect transistor comprises a gate structure comprising a gate dielectric and an intermediate electrode; and
the variable-capacitance capacitor comprises:
a lower capacitor plate comprising the intermediate electrode;
an upper capacitor plate vertically spaced from the lower capacitor plate; and
a variable-capacitance node dielectric located between the lower capacitor plate and the upper capacitor plate and comprising an electrical-field-programmable dielectric material providing a variable effective dielectric constant, and a data bit is stored as a dielectric state of the variable-capacitance node dielectric in the memory device.