| CPC H10B 63/30 (2023.02) [G11C 13/0002 (2013.01); H01L 21/28158 (2013.01); H01L 29/42364 (2013.01)] | 20 Claims |
|
1. A semiconductor device, comprising:
a first transistor comprising:
a first silicon layer;
a high-k gate dielectric layer disposed above the first silicon layer;
a first metal gate disposed above the high-k gate dielectric layer; and
a first source region and a first drain region disposed within the first silicon layer;
a second transistor comprising:
a second silicon layer;
a first silicon oxide layer disposed above the second silicon layer;
a plurality of first doped silicon gates disposed above the first silicon oxide layer;
a plurality of portions of a second doped silicon gate disposed above the first silicon oxide layer, wherein the plurality of first doped silicon gates and the plurality of portions of the second doped silicon gate are alternately arranged with each other; and
a second source region and a second drain region disposed within the second silicon layer; and
a memory component disposed above the first and second transistors, and electrically coupled to the second source region or the second drain region.
|