US 12,232,333 B2
Integrated circuit
Chieh-Fei Chiu, Tainan (TW); Wen-Ting Chu, Kaohsiung (TW); Yong-Shiuan Tsair, Tainan (TW); Yu-Wen Liao, New Taipei (TW); Chih-Yang Chang, Changhua County (TW); and Chin-Chieh Yang, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,483.
Application 18/361,483 is a division of application No. 17/032,155, filed on Sep. 25, 2020, granted, now 11,751,405.
Prior Publication US 2023/0380190 A1, Nov. 23, 2023
Int. Cl. H10N 70/20 (2023.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01); H10B 61/00 (2023.01); H10B 63/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01); H10N 70/00 (2023.01)
CPC H10B 63/30 (2023.02) [H10B 51/30 (2023.02); H10B 51/40 (2023.02); H10B 61/22 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); H10N 70/021 (2023.02); H10N 70/063 (2023.02); H10N 70/068 (2023.02); H10N 70/231 (2023.02); H10N 70/253 (2023.02); H10N 70/841 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a metal/dielectric layer having a first dielectric layer and a conductive feature in the first dielectric layer;
a second dielectric layer over the metal/dielectric layer;
a bottom electrode over the conductive feature and surrounded by the second dielectric layer, wherein the bottom electrode has a sidewall landing on a tapered sidewall of the second dielectric layer;
a resistance switch element over the bottom electrode; and
a top electrode over the resistance switch element.