US 12,232,331 B2
Memory devices with selector layer and methods of forming the same
Hung-Li Chiang, Taipei (TW); Jung-Piao Chiu, Kaohsiung (TW); Tzu-Chiang Chen, Hsinchu (TW); Yu-Sheng Chen, Taoyuan (TW); and Xinyu Bao, Fremont, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Oct. 3, 2023, as Appl. No. 18/479,836.
Application 18/479,836 is a continuation of application No. 17/737,032, filed on May 5, 2022, granted, now 11,805,662.
Application 17/737,032 is a continuation of application No. 16/885,231, filed on May 27, 2020, granted, now 11,342,380, issued on May 24, 2022.
Prior Publication US 2024/0032309 A1, Jan. 25, 2024
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01)
CPC H10B 63/24 (2023.02) [H10N 70/021 (2023.02); H10N 70/24 (2023.02); H10N 70/826 (2023.02); H10N 70/841 (2023.02); H10N 70/8822 (2023.02); H10N 70/8825 (2023.02); H10N 70/8828 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a memory cell disposed over a substrate;
a plurality of first work function layers disposed over the memory cell;
a selector layer disposed over the plurality of first work function layers;
a top electrode disposed over the selector layer, wherein a sidewall of the top electrode layer is flushed with a sidewall of the selector layer; and
a plurality of first barrier layers disposed between the first work function layers and the selector layer.