	US 12,232,330 B2
	Method for manufacturing semiconductor structure, semiconductor structure and semiconductor memory
Xiaoguang Wang, Hefei (CN); Huihui Li, Hefei (CN); Dinggui Zeng, Hefei (CN); Jiefang Deng, Hefei (CN); and Kanyu Cao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, Beijing (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN); and BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY, BeiJing (CN)
Filed on Jun. 1, 2022, as Appl. No. 17/805,004.
Application 17/805,004 is a continuation of application No. PCT/CN2022/077704, filed on Feb. 24, 2022.
Claims priority of application No. 202111009872.0 (CN), filed on Aug. 31, 2021.
Prior Publication US 2023/0061322 A1, Mar. 2, 2023
Int. Cl. H10B 61/00 (2023.01); H10N 50/01 (2023.01)

CPC H10B 61/00 (2023.02) [H10N 50/01 (2023.02)]

20 Claims

1. A method for manufacturing a semiconductor structure, comprising:

providing a substrate;

forming a magnetic tunnel junction (MTJ) structure and a first mask structure in sequence on the substrate;

performing a patterning process on the first mask structure to form a first pattern extending in a first direction;

transferring the first pattern to the MTJ structure;

forming a second mask structure on the MTJ structure;

performing a patterning process on the second mask structure to form a second pattern extending in a second direction, the first direction intersecting the second direction, and the first direction being not perpendicular to the second direction; and

performing a patterning process on the MTJ structure by utilizing the second pattern to form a cellular MTJ array, the first pattern and the second pattern together forming a cellular pattern.