US 12,232,328 B2
Memory devices
Meng-Han Lin, Hsinchu (TW); Mauricio Manfrini, Hsinchu County (TW); and Han-Jong Chia, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 6, 2023, as Appl. No. 18/296,385.
Application 18/296,385 is a division of application No. 17/155,093, filed on Jan. 22, 2021, granted, now 11,647,636.
Claims priority of provisional application 63/040,001, filed on Jun. 17, 2020.
Prior Publication US 2023/0255032 A1, Aug. 10, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/20 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/24 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 29/24 (2013.01); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
a multi-layer stack, comprising a plurality of first conductive lines stacked on one another and each extending along a first direction; and
a plurality of second conductive lines arranged in the first direction and at a first level above the plurality of first conductive lines, wherein the plurality of second conductive lines are each extending along a second direction perpendicular to the first direction, and widths of the plurality of second conductive lines are increased as the plurality of second conductive lines become close to a middle portion of the first level along the first direction.