| CPC H10B 51/20 (2023.02) [H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H10B 51/30 (2023.02)] | 34 Claims |
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1. A fabrication process, comprising:
forming an etch stop layer over a planar surface of a substrate;
forming an oxide layer above the etch stop layer;
forming a plurality of alternating layers of silicon oxide and a first material;
forming a plurality of shafts by etching the alternating layers of silicon oxide and the first material down to the etch stop layer;
forming a conformal channel silicon layer over sidewalls of the shafts;
forming a conformal gate oxide layer over the channel silicon layer;
forming a ferroelectric layer over the gate oxide layer; and
filling the shafts with a conductive material to form a gate electrode.
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