US 12,232,327 B2
Three-dimensional ferroelectric random-access memory (FeRAM)
Yung-Tin Chen, Taoyuan (TW)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Nov. 9, 2022, as Appl. No. 17/984,164.
Application 17/984,164 is a division of application No. 16/558,072, filed on Aug. 31, 2019, granted, now 11,515,330.
Claims priority of provisional application 62/846,418, filed on May 10, 2019.
Prior Publication US 2023/0147421 A1, May 11, 2023
Int. Cl. H01L 29/66 (2006.01); H01L 29/78 (2006.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H10B 51/30 (2023.02)] 34 Claims
OG exemplary drawing
 
1. A fabrication process, comprising:
forming an etch stop layer over a planar surface of a substrate;
forming an oxide layer above the etch stop layer;
forming a plurality of alternating layers of silicon oxide and a first material;
forming a plurality of shafts by etching the alternating layers of silicon oxide and the first material down to the etch stop layer;
forming a conformal channel silicon layer over sidewalls of the shafts;
forming a conformal gate oxide layer over the channel silicon layer;
forming a ferroelectric layer over the gate oxide layer; and
filling the shafts with a conductive material to form a gate electrode.