CPC H10B 43/30 (2023.02) [H01L 21/02129 (2013.01); H01L 21/02219 (2013.01); H01L 21/02236 (2013.01)] | 22 Claims |
1. A method of fabrication of a semiconductor device, comprising:
dividing a substrate into first and second regions;
forming a customizable oxide-nitride-oxide (ONO) stack in the first region, comprising:
performing at least one of a first radical oxidation and a first oxide deposition process steps in an atomic layer deposition (ALD) tool to form a tunnel dielectric layer overlying the substrate;
performing a plurality of silicon nitride deposition process steps in the ALD tool to form a multi-layer charge trapping (CT) layer, comprising:
determining process parameters of a first silicon nitride deposition process step of the plurality of silicon nitride deposition process steps to form a first CT sub-layer;
modifying at least one of the process parameters;
performing a second silicon nitride deposition process step to form a second CT sub-layer overlying the first CT sub-layer; and
performing at least one of a second radical oxidation and a second oxide deposition process steps in the ALD tool to form a blocking dielectric layer overlying the multi-layer CT layer in the first region, wherein the multi-layer CT layer includes at least three CT sub-layers, and wherein the process parameters of the plurality of silicon nitride deposition process steps are modified such that a top CT sub-layer that is adjacent to the blocking dielectric layer is the most oxygen-lean and a bottom CT sub-layer that is adjacent to the tunnel dielectric layer is the most oxygen-rich in the multi-layer CT layer.
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