US 12,232,323 B2
Three-dimensional semiconductor memory devices
Euntaek Jung, Seongnam-si (KR); JoongShik Shin, Suwon-si (KR); and JiHye Yun, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 21, 2023, as Appl. No. 18/515,536.
Application 18/515,536 is a continuation of application No. 17/825,619, filed on May 26, 2022, granted, now 11,839,084.
Application 17/825,619 is a continuation of application No. 16/999,511, filed on Aug. 21, 2020, granted, now 11,348,942, issued on May 31, 2022.
Application 16/999,511 is a continuation of application No. 16/192,859, filed on Nov. 16, 2018, granted, now 10,777,572, issued on Sep. 15, 2020.
Claims priority of application No. 10-2018-0050096 (KR), filed on Apr. 30, 2018.
Prior Publication US 2024/0090224 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 41/41 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H01L 23/522 (2006.01); H01L 29/66 (2006.01); H01L 49/02 (2006.01); H10B 41/40 (2023.01); H10B 41/50 (2023.01); H10B 43/10 (2023.01); H10B 43/30 (2023.01); H10B 43/50 (2023.01); H10B 69/00 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/28525 (2013.01); H01L 21/76868 (2013.01); H01L 23/528 (2013.01); H01L 23/53271 (2013.01); H01L 29/40114 (2019.08); H01L 29/40117 (2019.08); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/41 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 28/00 (2013.01); H01L 29/66833 (2013.01); H10B 41/40 (2023.02); H10B 41/50 (2023.02); H10B 43/10 (2023.02); H10B 43/30 (2023.02); H10B 43/50 (2023.02); H10B 69/00 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) semiconductor memory device comprising:
a horizontal semiconductor layer;
a source structure on the horizontal semiconductor layer, the source structure comprising a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer;
a first stack on the source structure, the first stack comprising a plurality of first electrodes vertically stacked on the source structure;
a second stack on the first stack, the second stack comprising a plurality of second electrodes vertically stacked on the source structure; a vertical semiconductor pattern penetrating the first and second stacks and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure; and
a common source structure penetrating the first and second stacks and the source structure and spaced apart from the vertical semiconductor pattern, the common source structure comprising:
a common source plug connected to the horizontal semiconductor layer; and
an insulating spacer disposed between the common source plug and the first and second stacks,
wherein the first source conductive pattern has a first thickness in a vertical direction perpendicular to a top surface of the horizontal semiconductor layer, the second source conductive pattern has a second thickness in the vertical direction, and the second thickness is different from the first thickness,
wherein the common source structure includes a first portion adjacent to the first source conductive pattern, a second portion adjacent to the second source conductive pattern, and a third portion adjacent to the horizontal semiconductor layer, and
wherein a width of the first portion is greater than a width of the second portion.