| CPC H10B 43/27 (2023.02) [H01L 23/5226 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02)] | 20 Claims |
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1. An integrated circuit device, comprising:
a memory structure comprising memory cells in rows, wherein the rows extend laterally and are vertically stacked;
gate structures extending laterally along each row and providing control gates for the memory cells in the row;
a semiconductor channel for a one of the memory cells, wherein the semiconductor channel is lateral to the control gate corresponding to the one of the memory cells;
a data storage structure for the one of the memory cells, wherein the data storage structure is between the semiconductor channel and the corresponding control gate;
a source line, wherein the source line has a first lateral bulge, extends vertically, and contacts the semiconductor channel in a first contact area; and
a drain line, wherein the drain line has a second lateral bulge, extends vertically, and contacts the semiconductor channel in a second contact area;
wherein the first lateral bulge is closer to the second lateral bulge than is the first contact area to the second contact area.
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