US 12,232,320 B2
Word line structure of three-dimensional memory device
Qiang Xu, Wuhan (CN); Fandong Liu, Wuhan (CN); Zongliang Huo, Wuhan (CN); Zhiliang Xia, Wuhan (CN); Yaohua Yang, Wuhan (CN); Peizhen Hong, Wuhan (CN); Wenyu Hua, Wuhan (CN); and Jia He, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Aug. 22, 2023, as Appl. No. 18/236,815.
Application 16/843,714 is a division of application No. 16/046,814, filed on Jul. 26, 2018, granted, now 10,651,192.
Application 18/236,815 is a continuation of application No. 17/509,891, filed on Oct. 25, 2021, granted, now 11,792,989.
Application 17/509,891 is a continuation of application No. 16/843,714, filed on Apr. 8, 2020, granted, now 11,222,903.
Application 16/046,814 is a continuation of application No. PCT/CN2018/077927, filed on Mar. 2, 2018.
Claims priority of application No. 201710132422.8 (CN), filed on Mar. 7, 2017.
Prior Publication US 2023/0413560 A1, Dec. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H10B 43/10 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01)
CPC H10B 43/27 (2023.02) [H01L 21/02164 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 29/0847 (2013.01); H01L 29/1037 (2013.01); H10B 43/10 (2023.02); H10B 43/30 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 43/50 (2023.02); H01L 21/02271 (2013.01); H01L 21/0262 (2013.01); H01L 21/28568 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate;
a stack comprising a first tier over the substrate and a second tier on the first tier, wherein each of the first tier and the second tier comprises gate material layers and insulating layers alternatingly arranged and extending along a first direction; and
a gate line slit extending along the first direction and dividing the stack into two portions,
wherein the stack comprises a connection portion that connects the two portions of the stack, the connection portion comprises at least two sub-connection portions along a second direction perpendicular to the first direction, the gate line slit comprises at least two portions along the first direction, and each sub-connection portion is between adjacent two portions of the gate line slit, a first sub-connection portion that connects the gate material layers of the first tier is different from a second sub-connection portion that connects the gate material layers of the second tier.