US 12,232,319 B2
Semiconductor memory device
Takahito Nishimura, Kuwana (JP); and Takuya Nishikawa, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 13, 2022, as Appl. No. 17/806,538.
Claims priority of application No. 2021-205073 (JP), filed on Dec. 17, 2021.
Prior Publication US 2023/0200069 A1, Jun. 22, 2023
Int. Cl. H10B 43/27 (2023.01); H10B 43/40 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 43/40 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a stacked body that includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked one by one and includes a stepped portion in which the plurality of conductive layers is processed in a stepped shape;
a first pillar that extends in a stacking direction of the stacked body in the stacked body away from the stepped portion in a first direction intersecting the stacking direction and forms a memory cell at each intersection with at least a part of the plurality of conductive layers; and
a plurality of second pillars that extends in the stacking direction in the stacked body in the stepped portion, wherein
each of the plurality of second pillars includes
a second insulating layer extending in the stacked body in the stacking direction,
a semiconductor layer covering a side wall of the second insulating layer,
a third insulating layer disposed in contact with a side wall of the semiconductor layer and covering the side wall of the semiconductor layer, and
a fourth insulating layer disposed in direct contact with a side wall of the third insulating layer and covering the side wall of the third insulating layer, and
the third and fourth insulating layers contain a same kind of material.