US 12,232,318 B2
Nonvolatile memory device
Jae Ho Ahn, Seoul (KR); Sung-Min Hwang, Hwaseong-si (KR); Joon-Sung Lim, Seongnam-si (KR); Bum Kyu Kang, Suwon-si (KR); and Sang Don Lee, Cheonan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 22, 2022, as Appl. No. 17/726,899.
Application 17/726,899 is a continuation of application No. 16/890,115, filed on Jun. 2, 2020, granted, now 11,315,947.
Claims priority of application No. 10-2019-0127725 (KR), filed on Oct. 15, 2019.
Prior Publication US 2022/0246643 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A nonvolatile memory device, comprising:
a mold structure that includes a plurality of word lines stacked on a substrate and first, second, and third string selection lines sequentially stacked on the plurality of word lines;
a plurality of channel structures that penetrates the mold structure and is connected to the substrate;
a first cutting region that cuts the mold structure;
a second cutting region that is spaced apart from the first cutting region in a first direction parallel to an upper surface of the substrate and that cuts the mold structure, the first and second cutting regions extending in a second direction intersecting the first direction, the first and second cutting regions being immediately adjacent to each other;
first, second and third cutting lines that extend in the second direction and cut at least one of the first, second and third string selection lines between the first cutting region and the second cutting region; and
a bit line on the mold structure extending in the first direction,
wherein the channel structures include first to fourth channel structures sequentially arranged in the first direction between the first cutting region and the second cutting region and electrically connected to the bit line.