CPC H10B 43/27 (2023.02) [H01L 29/40117 (2019.08); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/10 (2023.02)] | 26 Claims |
1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming a conductor tier comprising conductor material on a substrate, the conductor tier comprising etch-stop material spanning laterally-across and laterally-between multiple locations where individual channel-material-string constructions will be formed, the etch-stop material being of different composition from an upper portion of the conductor material;
forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier and the etch-stop material, material of the first tiers being of different composition from material of the second tiers;
the etch-stop material being formed to comprise (a) or (b), where
(a): laterally-opposing sides that taper laterally-inward moving deeper into the conductor tier; and
(b): laterally-opposing sides that are everywhere spaced laterally-inward of laterally-opposing sides of the laterally-spaced memory-block regions;
etching channel openings through the first tiers and the second tiers to stop on the etch-stop material; and
forming a channel-material-string construction in individual of the channel openings directly above the etch-stop material, the channel material of the channel-material-string construction directly electrically coupling to the conductor material in the conductor tier.
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