US 12,232,313 B2
Staircase structure in three-dimensional memory device and method for forming the same
Zhong Zhang, Wuhan (CN); Zhongwang Sun, Wuhan (CN); Wenxi Zhou, Wuhan (CN); and Zhiliang Xia, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on May 8, 2023, as Appl. No. 18/144,650.
Application 18/144,650 is a continuation of application No. 16/881,168, filed on May 22, 2020, granted, now 11,696,439.
Application 16/881,168 is a continuation of application No. PCT/CN2020/080670, filed on Mar. 23, 2020.
Prior Publication US 2023/0276620 A1, Aug. 31, 2023
Int. Cl. H10B 41/20 (2023.01); H10B 41/10 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/35 (2023.01)
CPC H10B 41/20 (2023.02) [H10B 41/10 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/35 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) memory device, comprising:
a memory array structure comprising a first memory array structure and a second memory array structure;
a staircase structure between the first memory array structure and the second memory array structure in a first lateral direction, the staircase structure comprising a first staircase zone and a second staircase zone; and
a first bridge structure between the first staircase zone and the second staircase zone in a second lateral direction perpendicular to the first lateral direction, the first bridge structure having a first top surface that is nominally flat;
a second bridge structure between the first staircase zone and the second staircase zone in the second lateral direction, the second bridge structure having a second top surface that is nominally flat,
wherein the first bridge structure and the second bridge structure are separated by a gate line slit structure,
wherein each of the first staircase zone and the second staircase zone comprises:
first sub-staircases and second sub-staircases arranged alternately, each of the first sub-staircases comprising ascending stairs at different depths, each of the second sub-staircases comprising descending stairs at different depths; and
at least one stair in each of the first sub-staircases and the second sub-staircases is connected to the first memory array structure and the second memory array structure through the at least one of the first bridge structure and the second bridge structure.