US 12,232,311 B2
Memory device having 2-transistor vertical memory cell
Srinivas Pulugurtha, Boise, ID (US); and Durai Vishak Nirmal Ramaswamy, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 10, 2023, as Appl. No. 18/388,769.
Application 18/388,769 is a continuation of application No. 17/961,282, filed on Oct. 6, 2022, granted, now 11,839,073.
Application 17/961,282 is a continuation of application No. 17/146,043, filed on Jan. 11, 2021, granted, now 11,581,319.
Application 17/146,043 is a continuation of application No. 16/722,813, filed on Dec. 20, 2019, granted, now 10,892,264.
Claims priority of provisional application 62/785,154, filed on Dec. 26, 2018.
Prior Publication US 2024/0196604 A1, Jun. 13, 2024
Int. Cl. G11C 11/40 (2006.01); G11C 11/4097 (2006.01); H10B 12/00 (2023.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4093 (2006.01)
CPC H10B 12/50 (2023.02) [G11C 11/4097 (2013.01); H10B 12/01 (2023.02); G11C 11/408 (2013.01); G11C 11/4091 (2013.01); G11C 11/4093 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a memory cell including:
a first transistor including a charge storage structure and a first channel region separated from the charge storage structure; and
a second transistor including a second channel region coupled to the charge storage structure, wherein the charge storage structure is between the second channel region and the first channel region;
a conductive region coupled to the first channel region;
a data line coupled to one of the first channel region and the second channel region; and
at least one access line separated from the first channel region and the second channel region.