| CPC H10B 10/125 (2023.02) [H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] | 19 Claims |
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1. A semiconductor storage device including a two-port SRAM cell, the two-port SRAM cell comprising:
a first transistor connected to a first power supply supplying a first voltage at one of its nodes, to a first node at the other node, and to a second node at its gate;
a second transistor connected to the first power supply at one of its nodes, to the second node at the other node, and to the first node at its gate;
a third transistor connected to the first node at one of its nodes, to a second power supply supplying a second voltage different from the first voltage at the other node, and to the second node at its gate;
a fourth transistor connected to the second node at one of its nodes, to the second power supply at the other node, and to the first node at its gate;
a fifth transistor connected to a first write bit line at one of its nodes, to the first node at the other node, and to a write word line at its gate;
a sixth transistor connected to a second write bit line at one of its nodes, to the second node at the other node, and to the write word line at its gate, the first write bit line and the second write bit line constituting a complementary bit line pair;
a seventh transistor connected to the second power supply at one of its nodes and to the second node at its gate; and
an eighth transistor connected to the other node of the seventh transistor at one of its nodes, to a first read bit line at the other node, and to a read word line at its gate,
wherein
the first to eighth transistors respectively include
first to eighth nanosheets extending in a first direction, and
first to eighth gate interconnects surrounding the first to eighth nanosheets in a second direction vertical to the first direction and in a third direction perpendicular to the first and second directions,
the sixth, first, third, and seventh nanosheets are formed in line in this order in the second direction,
the fourth, second, fifth, and eighth nanosheets are formed in line in this order in the second direction,
faces of the second, third, and fifth nanosheets on a first side as one of the opposite sides in the second direction are exposed from the second, third, and fifth gate interconnects, respectively,
faces of the first, fourth, sixth, seventh, and eighth nanosheets on a second side as the other side in the second direction are exposed from the first, fourth, sixth, seventh, and eighth gate interconnects, respectively,
the first side is the side on which the third nanosheet is opposed to the first nanosheet, and also the side on which the second nanosheet is opposed to the fourth nanosheet, and
the second side is the side on which the first nanosheet is opposed to the third nanosheet, and also the side on which the fourth nanosheet is opposed to the second nanosheet.
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